1. Field of the Invention
The invention relates to a method for manufacturing dynamic RAM (random access memory) one-transistor storage cells integrated in a semiconductor chip, consisting of one each integrated field-effect transistor and one integrated capacitor, in which the oxide structures are applied in a manner known per se, for instance, by means of locos processes by means of a photolithographically given pattern on a semiconductor surface.
2. Description of the Prior Art
In the preparation of such storage cells, one endeavors to generate capacitance as large as possible and at the same time, to reduce the area required on the chip.
To create capacitance as large as possible, a weakly doped semiconductor substrate is usually used and the insulator capacity under the capacitor is made as large as possible which, however, leads generally to a relatively small insulator layer thickness. The capacitor structures and the field-effect transistor structures are worked into the semiconductor body by means of photolithographic processes. However, in photolithographic processes, certain adjustment tolerances are given, below which one cannot go.
One-transistor cells generated thereby therefore require a certain amount of space on the semiconductor chip which cannot be reduced appreciably because of the adjustment tolerances of the photolithographic processes. Since however, the area required by storage cells in a chip is an important factor for their use in the construction of memories, it is desirable to reduce this space.